The present invention relates to an analog-to-digital (AD) converter and an analog-to-digital conversion method, and more specifically, to a technique to correct the influence of jitter of a sampling clock.
Recently, the performance of an AD converter has been improved remarkably; however, when a high-frequency input signal is subjected to AD conversion, there arises a serious problem of degradation of precision in which the jitter of a sampling clock causes an error of amplitude. The influence of jitter of a sampling clock is increased in a high-frequency signal and a large-amplitude signal, of which the slew rate of input signal is large, and the SNR (Signal to Noise Ratio) of an AD converter is degraded. In order to prevent such a problem from arising, it is necessary to reduce the jitter of a sampling clock; however, such a sampling clock is difficult to supply and particularly, there is a problem in that it is difficult to supply a sampling clock with small jitter on an Soc (System-on-Chip).
When an analog signal to be subjected to AD conversion is sampled at the rise of a sampling clock (it can also be sampled at the fall), the jitter of the sampling clock is the fluctuation of the rise in timing of the sampling clock from the reference timing. As described in, for example, K. Nose, M. Kajita, M. Mizuno, “A 1 ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling”, IEEE JSSC, vol. 41, no. 12, pp. 2911-2920 (December 2006) etc., the fluctuations include jitter of time difference from the reference (ideal) timing and jitter of the length of each cycle. The “time difference of the actual rise timing of clock from the reference timing” is defined as jitter.
FIG. 1 is a diagram explaining an error by the jitter of a sampling clock. As shown schematically, when sampled with an ideal sampling clock without jitter, an amplitude value shown by a circle of an input signal Ain is sampled; however, jitter is included in an actual sampling clock, and therefore, an amplitude value shown by a cross mark is sampled, and because of this, an error is produced in the sampled amplitude value, resulting in the production of an error in the output of AD conversion.
In order to discuss the influence of jitter, it is assumed that a voltage value V of the input signal Ain changes in a sinusoidal waveform with an amplitude A. Voltage signal V is expressed by the following expression as shown in FIG. 2B.V=A sin(2πfint)
The rate of change of voltage signal V is a derivative of V with respect to time, and therefore, expressed by the following expression as shown in FIG. 2C.dV/dt=2πfinA(2πfint)
The rate of change dV/dt is largest, i.e., the influence of jitter is largest when cos(2πfint)=1. Hereinafter, the case where the influence is largest is discussed, and therefore, dV/dt=2πfinA.
It is assumed that an AD converter is configured so that the analog input signal Ain is input to a sample and hold (S/H) circuit 1, sampled according to a clock CLK, and the held voltage is converted into a digital output signal Dout in an analog-to-digital conversion (ADC) part 2, as shown in FIG. 2D.
When a sampling clock includes jitter δt, an amplitude error dV that occurs in the sampling value is the gradient dV/dt multiplied by δt at most, and expressed by the following expression.dV=2πfinAδt 
From this, the SNR (Signal to Noise Ratio) of the AD converter is expressed as shown in FIG. 2F.SNRjitter=−20 log(2πfinAδt)
FIG. 3 is a diagram showing the change in SNR with respect to the magnitude of jitter for different frequencies fin of the input analog signal Ain based on the above expression. From the figure, it can be seen that the error caused by jitter becomes larger the greater the jitter and amplitude A are, and the higher the frequency fin is.